1. Field of the Disclosure
The disclosure relates to a chip stack. Particularly, the disclosure relates to a repairable multi-layer memory chip stack.
2. Description of Related Art
A three-dimensional (3D) chip integration technology can be used for reducing the wire length of interconnection to improve system performance. Regarding an electronic device having a regular structure, for example, a memory chip, therefore the memory capacity can be dramatically increased according to an existing chip fabrication process through the 3D chip integration technology without re-planning the layout of the chip and fabricating one or more new optical masks to meet the memory requirements for new hardware. In general, the 3D chip integration technology means that semiconductor chips are stacked in a same electric package by using a through-silicon-via (TSV) interconnection process. At least one redundant or spare memory block is generally disposed in internal of the memory chip in order to repair the memory chip.